<?xml version="1.0" encoding="UTF-8"?>
<article article-type="research-article" xml:lang="en-US" xmlns:xlink="http://www.w3.org/1999/xlink">
<front>
<journal-meta>
<journal-id journal-id-type="publisher">global-journal-of-research-in-engineering-f-electrical-electronic</journal-id>
<journal-title-group>
<journal-title>Global Journal of Research in Engineering - F: Electrical &amp; Electronic</journal-title>
</journal-title-group>
<issn publication-format="print">0975-5861</issn>
<issn publication-format="electronic">2249-4596</issn>
<publisher><publisher-name>Global Journals Publishing Group Incorporated</publisher-name></publisher>
<self-uri xlink:href="https://globaljournals.org/journal-seo-export/jats/115801.xml" />
</journal-meta>
<article-meta>
<article-id pub-id-type="publisher-id">115801</article-id>
<title-group>
<article-title>An Extensive Review of Emerging Technology Networks-On-Chip Proposals</article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author"><name><surname>Achballah</surname><given-names>Ahmed Ben</given-names></name><xref ref-type="aff" rid="aff1" />
</contrib>
</contrib-group>
<aff id="aff1">TUNISIA, University of Carthage</aff>
<pub-date publication-format="electronic" date-type="pub" iso-8601-date="2017-01-15">
<day>15</day>
<month>01</month>
<year>2017</year>
</pub-date>
<volume>17</volume>
<issue>F6</issue>
<abstract><p>Many synthesis works discussed emerging technology networks−on−chip (NoC) from different aspects. These works were and still are a solid foundation of the state of the art for emerging technology NoC research and practices. However, with respect to their quality and conciseness, the available literature is outdated or don’t give an extensive review of the available contributions in this area. In this paper, we iterate and discuss our findings in terms of research and practices for emerging technology NoC for the last ten years. The analyzed proposals are exposed chronologically. This will help to answer to the questions of when and how the concept was introduced, what is its present state and what the future directions are.</p></abstract>
<kwd-group kwd-group-type="author-generated">
<kwd>noc</kwd>
<kwd>on-chip interconnect</kwd>
<kwd>emerging technology noc</kwd>
<kwd>3d noc</kwd>
<kwd>onoc</kwd>
<kwd>photonic noc</kwd>
<kwd>winoc</kwd>
<kwd>rf−interconnect.</kwd>
</kwd-group>
<self-uri content-type="pdf" xlink:href="https://globaljournals.org/GJRE_Volume17/3-An-Extansive-Review-of-Emerging.pdf" />
<self-uri content-type="html" xlink:href="https://globaljournals.org/scholarly-articles/an-extensive-review-of-emerging-technology-networks-on-chip-proposals/" />
</article-meta>
</front>
<body>
<sec>
<title>Full Text</title>
<p>Many synthesis works discussed emerging technology networks−on−chip (NoC) from different aspects. These works were and still are a solid foundation of the state of the art for emerging technology NoC research and practices. However, with respect to their quality and conciseness, the available literature is outdated or don’t give an extensive review of the available contributions in this area. In this paper, we iterate and discuss our findings in terms of research and practices for emerging technology NoC for the last ten years. The analyzed proposals are exposed chronologically. This will help to answer to the questions of when and how the concept was introduced, what is its present state and what the future directions are.</p>
</sec>
</body>
</article>