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<journal-meta>
<journal-id journal-id-type="publisher">global-journal-of-research-in-engineering</journal-id>
<journal-title-group>
<journal-title>Global Journal of Research in Engineering</journal-title>
</journal-title-group>
<issn publication-format="print">0975-5861</issn>
<issn publication-format="electronic">2249-4596</issn>
<publisher><publisher-name>Global Journals Publishing Group Incorporated</publisher-name></publisher>
<self-uri xlink:href="https://globaljournals.org/journal-seo-export/jats/55651.xml" />
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<article-id pub-id-type="publisher-id">55651</article-id>
<title-group>
<article-title>Investigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics</article-title>
<subtitle>Performance Analysis of FDSOI and PDSOI MOSFETs</subtitle>
</title-group>
<contrib-group>
<contrib contrib-type="author"><name><surname>Chowdhury</surname><given-names>Towhid Adnan</given-names></name><xref ref-type="aff" rid="aff1" />
</contrib>
</contrib-group>
<aff id="aff1">BANGLADESH</aff>
<pub-date publication-format="electronic" date-type="pub" iso-8601-date="2023-08-12">
<day>12</day>
<month>08</month>
<year>2023</year>
</pub-date>
<volume>23</volume>
<issue>F2</issue>
<fpage>1</fpage>
<lpage>6</lpage>
<abstract><p>The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.</p></abstract>
<kwd-group kwd-group-type="author-generated">
<kwd>silicon on insulator</kwd>
<kwd>subthreshold slope</kwd>
<kwd>leakage current</kwd>
<kwd>threshold voltage</kwd>
<kwd>drain induced barrier lowering.</kwd>
</kwd-group>
<self-uri content-type="pdf" xlink:href="https://globaljournals.org/GJRE_Volume23/1-Investigation-the-Impact-of-Silicon-Film.pdf" />
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<title>Full Text</title>
<p>The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.</p>
</sec>
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