This paper presents design and implementation of TDC based on time stamping using current balanced logic (CBL) buffer in 0.35 μm CMOS technology. The CBL logic buffer provides smaller delay compared to widely used current starved inverter, allowing better resolution in a given technology node. The CBL buffer based tapped delay line (TDL) provides accurate reference timing signals for time stamping through latching their status by event signal. The time stamping is designed with dynamic range of 40 μs and allows tunable resolution with minimum value of 136 ps by varying CBL delay using off-chip reference voltage. Across process voltage & temperature (PVT) variations, by stabilizing the CBL delay with the help of delay lock loop (DLL), the attained resolution is 174 ps. This TDC is designed to work in two modes-Time Interval (TI) measurement mode and common stop multi-hit mode to enhance scope of its utilization.
This paper presents design and implementation of TDC based on time stamping using current balanced logic (CBL) buffer in 0.35 μm CMOS technology. The CBL logic buffer provides smaller delay compared to widely used current starved inverter, allowing better resolution in a given technology node. The CBL buffer based tapped delay line (TDL) provides accurate reference timing signals for time stamping through latching their status by event signal. The time stamping is designed with dynamic range of 40 μs and allows tunable resolution with minimum value of 136 ps by varying CBL delay using off-chip reference voltage. Across process voltage & temperature (PVT) variations, by stabilizing the CBL delay with the help of delay lock loop (DLL), the attained resolution is 174 ps. This TDC is designed to work in two modes- Time Interval (TI) measurement mode and common stop multi-hit mode to enhance scope of its utilization.