global-journal-of-research-in-engineering-f-electrical-electronic Global Journal of Research in Engineering - F: Electrical & Electronic 0975-5861 2249-4596 Global Journals Publishing Group Incorporated 89509 An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology BabuCh. Ashok RavindraJ.V.R. KishoreK. Lal INDIA, Swami Vivekananda Institute of Technology 15 01 2013 13 F14 27 30

Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders .

 average power leakage power delay DTMOS PDP. Full Text

Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].