A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution

Pooja Saxena

A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution

Pooja Saxena * §

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§ Homi Bhabha National Institute

A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution

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Abstract

This paper presents design and implementation of TDC based on time stamping using current balanced logic (CBL) buffer in 0.35 μm CMOS technology. The CBL logic buffer provides smaller delay compared to widely used current starved inverter, allowing better resolution in a given technology node. The CBL buffer based tapped delay line (TDL) provides accurate reference timing signals for time stamping through latching their status by event signal. The time stamping is designed with dynamic range of 40 μs and allows tunable resolution with minimum value of 136 ps by varying CBL delay using off-chip reference voltage. Across process voltage & temperature (PVT) variations, by stabilizing the CBL delay with the help of delay lock loop (DLL), the attained resolution is 174 ps. This TDC is designed to work in two modes-Time Interval (TI) measurement mode and common stop multi-hit mode to enhance scope of its utilization.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Pooja Saxena. 2015. "A Current Balanced Logic Buffer based Time-To-Digital Converter with Improved Resolution". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 15 (GJRE Volume 15 Issue F4).

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GJRE Volume 15 Issue F4

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

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Classification

GJRE-F Classification FOR Code: 290903

Submission ReceivedFebruary 4, 2015
Peer Review Double Blind
Handling Editor
Accepted March 2, 2015
Published March 15, 2015

Version of record

v1.2

Issue date

May 5, 2015

Language

English

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Article Matrices

Total Score: 103

Country: India

Subject: Global Journal of Research in Engineering

Authors: Pooja Saxena, K.Hari Prasad, V.B.Chandratre (PhD/Dr. count: 0)

View Count (all-time): 389

Total Views (Real + Logic): 1664

Total Downloads (simulated): 152

Publish Date: 2015 03, Sun

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Total Views: 1.7K

Total Downloads: 152

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