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As chip density keeps doubling during each course of generation, the use of NoC has become an integral part of modern microprocessors and a very prevalent architectural feature of all types of SoCs. To meet the ever expanding communication challenges, diverse and novel NoC solutions are being developed which rely on accurate modeling and simulations to evaluate the impact and analyze their performances. Consequently, this aggravates the need to rely on simulation tools to probe and optimize these NoC architectures. In this work, we present NC-G-SIM (Network on Chip-Generic-SIMulator), a highly flexible, modular, cycle-accurate, configurable simulator for NoCs. To make NC-G-SIM suitable for advanced NoC exploration, it is made highly generic that supports extensive range of cores in any kind of topology whether 2D, 3D or irregular. Simulation results have been evaluated in terms of latencies, throughput and the amount of energy consumed during the simulation period at different levels.
Kartika Vyas, Naveen Choudhary, Dharm Singh. 2013. "NC-G-SIM: A Parameterized Generic Simulator for 2D-Mesh, 3D-Mesh & Irregular On-chip Networks with Table-based Routing". Global Journal of Computer Science and Technology - E: Network, Web & Security GJCST-E Volume 13 (GJCST Volume 13 Issue E14).
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
v1.2
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Total Score: 143
Country: India
Subject: Global Journal of Computer Science and Technology
Authors: Kartika Vyas, Naveen Choudhary, Dharm Singh (PhD/Dr. count: 0)
View Count (all-time): 395
Total Views (Real + Logic): 2963
Total Downloads (simulated): 187
Publish Date: 2013 01, Tue
Monthly Totals (Real + Logic):
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