Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip

Prachi Agarwal; Dr. Anil Kumar Sharma; Adesh Kumar

Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip

Prachi Agarwal * §

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Dr. Anil Kumar Sharma

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Adesh Kumar

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University of Petroleum & Energy Studies, Dehradun I...

Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip

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Abstract

The solution for the multiprocessor system architecture is Application specific Network on Chip (NOC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NOC can beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. The paper emphasizes on the network on chip modeling and synthesis of 2D network and intercommunication among multilevel 2D networks. NOC synthesis environment provides transaction level network modeling and address all the requirements together in an integrated chip. In the paper consideration is done for 2D, 8 x 8 network and similar networks are considered which are identified by their specific network address. NOC chip is developed using VHDL programming language. Design is implemented in Xilinx 14.2 VHDL software, functional simulation is carried out in Modelsim 10.1 b, student edition and synthesis process is carried out on Digilent Sparten -3E FPGA.

References

20 Cites in Article

Reference Format

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Prachi Agarwal, Dr. Anil Kumar Sharma, Adesh Kumar. 1969. "Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip". Global Journal of Computer Science and Technology - E: Network, Web & Security GJCST-E Volume 13 (GJCST Volume 13 Issue E12).

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GJCST Volume 13 Issue E12

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

application spec field programmable gate array (FPGA)network on chip (NOC)very high speed integrated circuit hardware description language (VHDL)

Classification

GJCST-E Classification C.2.1

Submission ReceivedDecember 8, 2012
Peer Review Double Blind
Handling Editor
Accepted January 4, 2013
Published January 15, 2013

Version of record

v1.2

Issue date

October 15, 2013

Language

English

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Article Matrices

Total Score: 148

Country: India

Subject: Global Journal of Computer Science and Technology

Authors: Prachi Agarwal, Dr. Anil Kumar Sharma, Adesh Kumar (PhD/Dr. count: 1)

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Publish Date: 2013 01, Tue

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