Research
Reduction of Power Consumption using Different Coding Schemes using FPGA in NOC
Network-On-Chip (NoC) is used as a main part of a system. NoC overcomes traditional System-On-Chip (SoC) problems. Because, SoC has problems like cost, design risk, more complexity and more power consumption. In software part, Xilinx ISE Design suite 14.5 with VHDL programming is used. It is simple programming language. In hardware part, FPGA of Spartan 3E family is used. It is advanced 90nm technology. It is world’s the cheapest FPGA family. It has 500K gates and 40 LUTs. It has lowest cost per logic. Its better advantage is that it is designed for more volume-to-market. Power consumption of given system is compared with previous system. From output power analysis chart, it is concluded that given system has lower power consumption than previous system. Power consumption of gray to binary conversion block of previous system is nearly equal to power consumption of present (given) whole system. This proves that there is a great reduction in power consumption in the system.
