FPGA Implementation of NPSF Testing Using Block Code Technique

α
K.L.V.Ramana Kumari
K.L.V.Ramana Kumari
σ
M. Asha Rani
M. Asha Rani
ρ
N.Balaji
N.Balaji
Ѡ
SK. Salauddeen
SK. Salauddeen

Send Message

To: Author

FPGA Implementation of NPSF Testing Using Block Code Technique

Article Fingerprint

ReserarchID

9633B

FPGA Implementation of NPSF Testing Using Block Code Technique Banner

AI TAKEAWAY

Connecting with the Eternal Ground
  • English
  • Afrikaans
  • Albanian
  • Amharic
  • Arabic
  • Armenian
  • Azerbaijani
  • Basque
  • Belarusian
  • Bengali
  • Bosnian
  • Bulgarian
  • Catalan
  • Cebuano
  • Chichewa
  • Chinese (Simplified)
  • Chinese (Traditional)
  • Corsican
  • Croatian
  • Czech
  • Danish
  • Dutch
  • Esperanto
  • Estonian
  • Filipino
  • Finnish
  • French
  • Frisian
  • Galician
  • Georgian
  • German
  • Greek
  • Gujarati
  • Haitian Creole
  • Hausa
  • Hawaiian
  • Hebrew
  • Hindi
  • Hmong
  • Hungarian
  • Icelandic
  • Igbo
  • Indonesian
  • Irish
  • Italian
  • Japanese
  • Javanese
  • Kannada
  • Kazakh
  • Khmer
  • Korean
  • Kurdish (Kurmanji)
  • Kyrgyz
  • Lao
  • Latin
  • Latvian
  • Lithuanian
  • Luxembourgish
  • Macedonian
  • Malagasy
  • Malay
  • Malayalam
  • Maltese
  • Maori
  • Marathi
  • Mongolian
  • Myanmar (Burmese)
  • Nepali
  • Norwegian
  • Pashto
  • Persian
  • Polish
  • Portuguese
  • Punjabi
  • Romanian
  • Russian
  • Samoan
  • Scots Gaelic
  • Serbian
  • Sesotho
  • Shona
  • Sindhi
  • Sinhala
  • Slovak
  • Slovenian
  • Somali
  • Spanish
  • Sundanese
  • Swahili
  • Swedish
  • Tajik
  • Tamil
  • Telugu
  • Thai
  • Turkish
  • Ukrainian
  • Urdu
  • Uzbek
  • Vietnamese
  • Welsh
  • Xhosa
  • Yiddish
  • Yoruba
  • Zulu

Abstract

This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

References

12 Cites in Article
  1. D Michael Lee,Bushnell,D Vishwani (2002). Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits.
  2. M Miron Abramovici,Melvin Breuer,Arthur Friedmaan (2002). Digital Systems Testing and Testable Design.
  3. K.-L Cheng,M.-F Tsai,C.-W Wu (2002). Neighborhood pattern-sensitive fault testing and diagnostics for random access memories.
  4. A Vandegoor (1991). Testing Semiconductor Memories: Theory and Practice.
  5. Yu-Jen Huang,Jin-Fu Li (null). Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.
  6. Je-Hoon Lee,Min-Jeong Jeon,Sang Kim (2012). Uniform Random Number Generator Using Leap-Ahead LFSR Architecture.
  7. A Van De Goor (1991). Testing Semiconductor Memories: Theory and Practice.
  8. K Cheng,M Tsai,C Wu (2002). Neighborhood Pattern Sensitive Fault Testing and Diagnostics for Random-Access Memories.
  9. K Cheng,C.-W Wu (2001). Efficient neighborhood pattern sensitive fault test algorithms for semiconductor memories.
  10. S Yarmolik,I Mrozek (2000). Multi Background Memory Testing.
  11. Nexys4 DDR FPGA xilix user guide.
  12. K Ramana Kumari,Asha Rani,Balaji (2017). FPGA implementation of memory design and testing.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

K.L.V.Ramana Kumari. 2018. \u201cFPGA Implementation of NPSF Testing Using Block Code Technique\u201d. Global Journal of Computer Science and Technology - G: Interdisciplinary GJCST-G Volume 18 (GJCST Volume 18 Issue G3): .

Download Citation

Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords
Classification
GJCST-G Classification: D.2.5
Version of record

v1.2

Issue date

June 9, 2018

Language
en
Experiance in AR

Explore published articles in an immersive Augmented Reality environment. Our platform converts research papers into interactive 3D books, allowing readers to view and interact with content using AR and VR compatible devices.

Read in 3D

Your published article is automatically converted into a realistic 3D book. Flip through pages and read research papers in a more engaging and interactive format.

Article Matrices
Total Views: 5802
Total Downloads: 1664
2026 Trends
Related Research

Published Article

This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

Our website is actively being updated, and changes may occur frequently. Please clear your browser cache if needed. For feedback or error reporting, please email [email protected]

Request Access

Please fill out the form below to request access to this research paper. Your request will be reviewed by the editorial or author team.
X

Quote and Order Details

Contact Person

Invoice Address

Notes or Comments

This is the heading

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo.

High-quality academic research articles on global topics and journals.

FPGA Implementation of NPSF Testing Using Block Code Technique

K.L.V.Ramana Kumari
K.L.V.Ramana Kumari
M. Asha Rani
M. Asha Rani
N.Balaji
N.Balaji
SK. Salauddeen
SK. Salauddeen

Research Journals