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This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.
K.L.V.Ramana Kumari. 2018. \u201cFPGA Implementation of NPSF Testing Using Block Code Technique\u201d. Global Journal of Computer Science and Technology - G: Interdisciplinary GJCST-G Volume 18 (GJCST Volume 18 Issue G3): .
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
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Total Score: 104
Country: India
Subject: Global Journal of Computer Science and Technology - G: Interdisciplinary
Authors: K.L.V.Ramana Kumari, M. Asha Rani, N.Balaji, SK. Salauddeen (PhD/Dr. count: 0)
View Count (all-time): 239
Total Views (Real + Logic): 5802
Total Downloads (simulated): 1664
Publish Date: 2018 06, Sat
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This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.
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