FPGA Implementation of QMF for Equalizer Application of Wireless Communication Channel

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P.Harika
P.Harika
2
A.pravin
A.pravin
1 BVC Engineering College,JNTU Kakinada

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In this paper a Quadrature Mirror Filter is implemented in VHDL, for wireless communication applications. The Quadrature Mirror Filter (QMF) basically is a parallel combination of a High Pass Filter (HPF) and Low Pass Filter (LPF), which performs the action of frequency subdivision by splitting the signal spectrum into two spectra. The QMF implementation is carried out on FPGA platform. The Xilinx IP Core generator will be used for instantiating the standard Xilinx parts. Xilinx ISE will be used to carry out the synthesis and bit file generation. The obtained Synthesis Report for implemented QMF will be used to analyze the occupied area and power dissipation. The study and implementation will be aimed to realize the equalizer for wireless communication system. Modelsim Xilinx Edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis and bit file generation. The Xilinx Chip scope will be used to test the results on Spartan 3E 500K FPGA board.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

P.Harika. 2011. \u201cFPGA Implementation of QMF for Equalizer Application of Wireless Communication Channel\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 11 (GJRE Volume 11 Issue F6): .

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Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

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v1.2

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November 15, 2011

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English

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In this paper a Quadrature Mirror Filter is implemented in VHDL, for wireless communication applications. The Quadrature Mirror Filter (QMF) basically is a parallel combination of a High Pass Filter (HPF) and Low Pass Filter (LPF), which performs the action of frequency subdivision by splitting the signal spectrum into two spectra. The QMF implementation is carried out on FPGA platform. The Xilinx IP Core generator will be used for instantiating the standard Xilinx parts. Xilinx ISE will be used to carry out the synthesis and bit file generation. The obtained Synthesis Report for implemented QMF will be used to analyze the occupied area and power dissipation. The study and implementation will be aimed to realize the equalizer for wireless communication system. Modelsim Xilinx Edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis and bit file generation. The Xilinx Chip scope will be used to test the results on Spartan 3E 500K FPGA board.

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FPGA Implementation of QMF for Equalizer Application of Wireless Communication Channel

P.Harika
P.Harika BVC Engineering College,JNTU Kakinada
A.pravin
A.pravin

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