Method to Minimize Data losses in multi stage Flip Flop
In complex digital circuits the clock arrives at next stages before the data pulses arrives to the next stage. The clock pulse must be inserted to activate the digital circuits at any stage starting from first stage. But due to unsynchronization between clock pulse and data there is a chance of miss hitting in the next stages. This leads improper data transmissions in complex systems. It creates data losses in transmission. In the present work a gate controlled clock scheme is proposed to increase data hitting ratio.
