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This article presents energy efficient fused multiplyadd for multimedia applications. Low cost, low power and high performance factors diddle the design of many microprocessors directed to the low-power figuring market. The floating point unit occupies a significant percentage of the silicon area in a microprocessor due to its wide data bandwidth and the area occupied by the multiply array. The fused floating-point multiply-add unit is utilitarian for digital signal processing (DSP) applications such as fast Fourier transform (FFT) and discrete cosine transform (DCT). The proposed designs are implemented for single precision and synthesized with a 45-nm standard cell library. To improve the performance of the fused floating point multiply-add unit, we are supervening upon leading zero anticipation with the novel leading zero detection, as the novel leading one detection algorithm allowing us to significantly reduce the anticipation failure rates.
Mandala Rakesh Raj. 2015. \u201cEnergy Efficient FMA for Embedded Multimedia Application\u201d. Global Journal of Research in Engineering - J: General Engineering GJRE-J Volume 14 (GJRE Volume 14 Issue J6).
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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Total Score: 102
Country: India
Subject: Global Journal of Research in Engineering - J: General Engineering
Authors: Mandala Rakesh Raj, Ms S. Sujana (PhD/Dr. count: 0)
View Count (all-time): 214
Total Views (Real + Logic): 4425
Total Downloads (simulated): 2136
Publish Date: 2015 01, Tue
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This study aims to comprehensively analyse the complex interplay between
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