Research
Area Optimized High Throughput IDMWT/DMWT Processor for OFDM on Virtex-5 FPGA
OFDM is one of the most popular modulation techniques that is been widely used in most of the wireless and wired communication links. The OFDM architecture consists of QAM modulator and orthogonal frequency modulator. In this work we propose DMWT based orthogonal frequency modulator for achieving higher BER. The IDMWT architecture is designed considering N=4, thus the preprocessing unit converts the QAM samples of N to 2N and is modulated using DMWT filters. The filtered output is further transmitted and is received at the receiver. During the post processing, N samples are extracted by use of DMWT demodulation technique. The complex architecture of IDMWT and DMWT are reduced for its complexity and speed by the modified architecture. The DMWT architecture is modified for FPGA implementation improving the area, power and speed performances. The modified DMWT architecture is implemented on VirtexII pro FPGA which operates at 300MHz frequency and occupies area of less than 1%, with power consumption less than 28mW. The proposed design is suitable for real time and low power applications.
Modified Lifting Based DWT/IDWT Architecture for OFDM on Virtex-5 FPGA
future Wireless communication requires high performance and high speed integrated data, audio, video and multimedia services. This performance is achieved using discrete wavelet transforms in terms of ISI and bandwidth compatibility over FFT based OFDM. Where FFT based OFDM has very compact spectral utilization which cannot satisfy the future needs. This project proposes implementation of new modified lifting wavelet transform for designing wavelets and performing the transform. By implementing LDWT, it is able to increase the spectral efficiency and also decrease the bit error rate. This paper presents a performance measure of mean squared error by using lifting wavelet transform. This paper shows that DWT-OFDM outperformed FFT-OFDM by approximately 6dB gain in BER, Haar wavelet showed best performance over other wavelets by approximately 2dB. However, computation complexity of DWT restricts use of DWT for OFDM due to its hardware requirements on VLSI platform. In this work, lifting based DWT is modified and a new architecture is derived that can compute DWT in less than 3.429ns, and consumes power of less than 28mW. The modified DWT is realized on Virtex II FPGA and occupies resources less than 114 slices. Thus the proposed DWT architecture is suitable for OFDM application.
