Research
Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology
Article
September 13, 2016
In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.
