Dr. M. Nagabushanam
VLSI B.2 ARITHMETIC AND LOGIC STRUCTURES , B.3 MEMORY STRUCTURES, B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS, B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION , B.6 LOGIC DESIGN, B.7 INTEGRATED CIRCUITS Arithmetic and Logic Structures Memory Structures Input/Output and Data Communications Register-Transfer-Level Implementation Logic Design Integrated Circuits Analog and Mixed-Signal Circuit Design Advanced Data Compression Techniques VLSI and FPGA Design Techniques Biomedical Engineering Computer Vision and Pattern Recognition Electrical and Electronic Engineering

Bio

Dr. M. Nagabushanam is an Assistant Professor in the Department of Electronics and Communication Engineering at M.S. Ramaiah Institute of Technology, Bangalore, India. He is also affiliated with Anna University, Coimbatore, India, where he completed his Ph.D. in VLSI in 2017. With over 30 publications and 200 citations, his research spans VLSI design, image compression, and low-dropout regulators. He has an h-index of 10 and i10-index of 10, and serves as a reviewer for international journals. His work on fast implementation of lifting-based DWT architecture for image compression and capacitor-less LDO regulators highlights his contributions to efficient analog and digital systems.

Educational Journey

Anna University, Chennai

Ph.D • VLSI

2017

Visvesvaraya Technological University, Belgaum

M.Tech • Electronics Engineering

2003

Bangalore University

B.E. • Electronics Engineering

1997

Experience

M.S. Ramaiah Institute of Technology

Assistant Professor

0 - 0 • Electronics and Communication Engineering

0 - 0

Editors Role

Reviewer

GJCST

2018 -

Research

Fast Implementation of Lifting Based DWT Architecture For Image Compression

Article July 31, 2012

Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using 130nm Technology. 2D DWT architecture based on lifting scheme architecture uses multipliers and adders, thus consuming power. This paper addresses power reduction in multiplier by proposing a modified algorithm for BZFAD multiplier. The proposed BZFAD multiplier is 65% faster and occupies 44% less area compared with the generic multipliers. The DWT architecture designed based on modified BZFAD multiplier achieves 35% less power reduction and operates at frequency of 200MHz with latency of 1536 clock cycles for 512x512 image. The developed DWT can be used as an IP for VLSI implementation.