Research
Six Phase Optimal Sequence Design for Mimo Radar
Radar applications desire a set of sequences with discretely peaky autocorrelation and pair_wise cross correlation. Invade such sequences is a combinal problem. If the autocorrelation and cross correlation are convenient in the a periodic sense then there are hardly any theoretical aids available thus the problem of signal design referred to above is a defying problem for which many global optimization algorithms like ant colony optimization ,artificial bee colony (ABC) algorithm and particle swarm optimization algorithm were reported in the literature. The paper intent at gadget of an efficient optimization algorithm is design to find an optimal pulse compression code useful for radar applications .The proposed optimization algorithm particle swarm optimization algorithm for identifying the optimal pulse compression codes and it is a real-time signal processing solution which identifies optimal sequences.
FPGA Implementation of High Speed Radar Signal Processing
Electronic support measure (ESM) system or Electronic Warfare Support (ES), is the subdivision of EW involving actions tasked by, or under direct control of, an operational commander to search for, intercept, identify, and locate or localize sources of intentional and unintentional radiated electromagnetic (EM) energy for the purpose of immediate threat recognition, targeting, planning, and conduct of future operations. To test an ESM system field environment is created by using various equipment and design tools.Testing a system is important part of designing and manufacturing a system and it is necessary in any field. To test an ESM system, it is difficult to test it near the theater of war. Testing an ESM system in the theater of war may result in expose of our information to the opponent nations. Therefore, in order to test an ESM system an artificial environment is created by using various equipment and design tools.
Bite Controller for ESM Systems
Electronic Support measures (ESM) system is used to measure the parameters of radar emission in the operating frequency range along with pulse width, pulse repetition frequency, antenna scan period, signal strength, direction of arrival and more. These systems are installed in warships, aircrafts and submarines. The radar parameters along with their threat levels are to be made available to operator during the peace and wartime operations. In the modern ESM systems these parameters are to be measured instantaneously with great accuracies and instantaneously for tactical purposes. Different techniques are used for measuring different parameters of radar signals. Receiver measure these parameters in various parallel circuits and ensure the entire measured data is available less than 200ns for each pulse which is required for further processing. The BITE processor controls various operations of these parallel receivers. It controls the operation of system to ensure reliable performance. The BITE processor receives the signal from the ESM processor and generates it in the specified number of bits. It also interfaces ESM processors and antenna processors.
FPGA based Solution for the Identification of RADAR Pulse Sequences for Defense Applications
The main objective of this paper is to design a generalized architecture for polyphase code identification used in RADAR signal processing applications. The proposed VLSI architecture will identify the type of a given polyphase code, amount of phase change and number of phase changes. RADAR signal processing applications require a set of sequences with individually peaky autocorrelation and pair wise cross correlation. Obtaining such sequences is a combinatorial problem. This paper aims at implementation of an efficient VLSI system for the design of polyphase codes identification useful for RADAR applications. The VLSI system is implemented on the field programmable gate array as it provides the flexibility of reconfigurability and reprogrammability and it is a real time signal processing solution which identifies the polyphase codes. The simulation results and the FPGA implementation shows the successful code identification, amount of phase, number of phase changes for a given input sequence.
