Research
Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic
A digital clock has been designed at gate level and is being presented in this paper. The clock architecture consists of three major blocks SECOND,MINUTE and HOUR. The architecture is the amalgam both of synchronous and asynchronous logic. All the flip-flops at each block run synchronously. The triggering operation of a block is asynchronous in nature. It serves the design requiring lower power consumption, provides lesser noise and electromagnetic interference, lower delay and greater throughput. The clock is designed at Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and Simulated by Vegilogger Pro 6.5.
FPGA based sigma delta modulator design for biomedical application using Verilog HDL
This paper proposes the design of micro power Sigma-delta modulator with using verilog HDL based on been mapped on small commercially available FPGAs (Field Programmable Gate Arrays). This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electrocardiogram(ECG),Electroencephalogram(EEG) etc. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. In this second order sigma delta modulator simulation result there is no distortion. It is very suitable for low power application of biomedical instrument design.
