Neural Networks and Rules-based Systems used to Find Rational and Scientific Correlations between being Here and Now with Afterlife Conditions
Neural Networks and Rules-based Systems used to Find Rational and
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Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant area overhead, consume a large power consumption, and have a large propagation delay. In this paper, a pseudo-PMOS logic is presented for the realization of wide fan-in NAND gates in a manner similar to the realization of wide fan-in NOR gates using the pseudo-NMOS logic. The circuit design issues of this family are discussed. Also, it is compared with the conventional CMOS logic from the points of view of the area, the average propagation delay, the average power consumption, and the logic swing using a proper figure of merit. The effects of technology scaling and process variations on this family are investigated. Simulation results verify the enhancement in performance in which the 45 nm CMOS technology is adopted.
Sherif M. Sharroush. 2017. \u201cA Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 17 (GJRE Volume 17 Issue F7): .
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
The methods for personal identification and authentication are no exception.
Total Score: 101
Country: Egypt
Subject: Global Journal of Research in Engineering - F: Electrical & Electronic
Authors: Sherif M. Sharroush (PhD/Dr. count: 0)
View Count (all-time): 221
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Publish Date: 2017 11, Mon
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Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant area overhead, consume a large power consumption, and have a large propagation delay. In this paper, a pseudo-PMOS logic is presented for the realization of wide fan-in NAND gates in a manner similar to the realization of wide fan-in NOR gates using the pseudo-NMOS logic. The circuit design issues of this family are discussed. Also, it is compared with the conventional CMOS logic from the points of view of the area, the average propagation delay, the average power consumption, and the logic swing using a proper figure of merit. The effects of technology scaling and process variations on this family are investigated. Simulation results verify the enhancement in performance in which the 45 nm CMOS technology is adopted.
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