A Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates

A Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates

Sherif M. Sharroush

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Port Said University

A Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates

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Abstract

Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant area overhead, consume a large power consumption, and have a large propagation delay. In this paper, a pseudo-PMOS logic is presented for the realization of wide fan-in NAND gates in a manner similar to the realization of wide fan-in NOR gates using the pseudo-NMOS logic. The circuit design issues of this family are discussed. Also, it is compared with the conventional CMOS logic from the points of view of the area, the average propagation delay, the average power consumption, and the logic swing using a proper figure of merit. The effects of technology scaling and process variations on this family are investigated. Simulation results verify the enhancement in performance in which the 45 nm CMOS technology is adopted.

References

14 Cites in Article

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Sherif M. Sharroush. 2017. \u201cA Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 17 (GJRE Volume 17 Issue F7).

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GJRE Volume 17 Issue F7

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

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Classification

GJRE-F Classification FOR Code: 090699

Submission ReceivedDecember 9, 2016
Peer Review Double Blind
Handling Editor
Accepted January 2, 2017
Published January 15, 2017

Version of record

v1.2

Issue date

November 13, 2017

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Article Matrices

Total Score: 101

Country: Egypt

Subject: Global Journal of Research in Engineering - F: Electrical & Electronic

Authors: Sherif M. Sharroush (PhD/Dr. count: 0)

View Count (all-time): 259

Total Views (Real + Logic): 3332

Total Downloads (simulated): 1749

Publish Date: 2017 11, Mon

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Total Views: 3332

Total Downloads: 1749

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