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The main contribution of this paper is an exact common sub expression elimination algorithm for the optimum sharing of partial terms in multiple constant multiplications (MCMs).Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers we have proposed the anti symmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. It was observed that the proposed algorithm obtains better solutions in terms of area than the algorithms designed for the MCM problem and the optimization of area problem in a digit-serial MCM operation at gate-level.
Maloth Santhoshi. 2015. \u201cAn Efficient Implementation of Digit FIR Filters using Memory based Realization\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F9): .
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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Total Score: 103
Country: India
Subject: Global Journal of Research in Engineering - F: Electrical & Electronic
Authors: Maloth Santhoshi, Mrs. E P Vanetha, P.Srikanth (PhD/Dr. count: 0)
View Count (all-time): 202
Total Views (Real + Logic): 4425
Total Downloads (simulated): 2179
Publish Date: 2015 01, Fri
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The main contribution of this paper is an exact common sub expression elimination algorithm for the optimum sharing of partial terms in multiple constant multiplications (MCMs).Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers we have proposed the anti symmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. It was observed that the proposed algorithm obtains better solutions in terms of area than the algorithms designed for the MCM problem and the optimization of area problem in a digit-serial MCM operation at gate-level.
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