An Efficient Implementation of Digit FIR Filters using Memory based Realization

Maloth Santhoshi; Mrs. E P Vanetha; P.Srikanth

An Efficient Implementation of Digit FIR Filters using Memory based Realization

Maloth Santhoshi * §

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Mrs. E P Vanetha §

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P.Srikanth §

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§ Vardhaman College of Engineering

An Efficient Implementation of Digit FIR Filters using Memory based Realization

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Abstract

The main contribution of this paper is an exact common sub expression elimination algorithm for the optimum sharing of partial terms in multiple constant multiplications (MCMs).Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers we have proposed the anti symmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. It was observed that the proposed algorithm obtains better solutions in terms of area than the algorithms designed for the MCM problem and the optimization of area problem in a digit-serial MCM operation at gate-level.

References

11 Cites in Article

Reference Format

1. A Novel Architecture of LUT Design Optimization for DSP Application.
2. Hardware Efficient Approach for Memoryless- Based Multiplication and Its Application to FIR Filter.
3. L. Aksoy,C. Lazzari ”Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool” re with INESC-ID, Lisbon 1000-029, Portugal (e-mail:levent@algos. inesc id.pt; [email protected] inesc-id.pt, 1000-1029.
4. Shen-Fu Hsiao,Jun-Hong Jian,Ming-Chih Chen Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication Accumulation.
5. L. Aksoy,E. Costa,P. Flores,J. Monteiro (2007). Optimization of Area in Digital FIR Filters using Gate-Level Metrics. Proc. DAC, 2007, 420-423.
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7. Levent Aksoy,Cristiano Lazzari,Eduardo Costa,Paulo Flores,José Monteiro (2011). Efficient shift-adds design of digit-serial multiple constant multiplications. Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011, 61-66.
CrossRef DOI
8. L. Aksoy,E. Costa,P. Flores,J. Monteiro (2008). Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6), 1013-1026.
CrossRef DOI
9. Pramod Meher (2009). LUT Optimization for Memory-Based Computation Pramod Kumar Meher, Senior Member, IEEE Manuscript received June 25, 2009; revised November 14, 2009. Current version published April
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11. (2008). Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level.

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Maloth Santhoshi, Mrs. E P Vanetha, P.Srikanth. 2015. "An Efficient Implementation of Digit FIR Filters using Memory based Realization". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue 45 (F9)).

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GJRE Volume 14 Issue 45 (F9)

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

digital signal processing (DSP)finite impulse response (FIR) filter lut-based computing multiple constant multiplication VLSI design

Classification

GJRE-F Classification FOR Code: 090699

Submission ReceivedDecember 11, 2013
Peer Review Double Blind
Handling Editor
Accepted January 4, 2014
Published December 1, 2014

Version of record

v1.2

Issue date

December 1, 2014

Language

English

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Article Matrices

Total Score: 103

Country: India

Subject: Global Journal of Research in Engineering - F: Electrical & Electronic

Authors: Maloth Santhoshi, Mrs. E P Vanetha, P.Srikanth (PhD/Dr. count: 0)

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Publish Date: 2014 11, Wed

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