An Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks

α
Samta Jain
Samta Jain
σ
Vaishali Sodani
Vaishali Sodani
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Naveen Choudhary
Naveen Choudhary
α Maharana Pratap University of Agriculture and Technology Maharana Pratap University of Agriculture and Technology

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An Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks

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Abstract

On-chip communication, modular, scalable packet-switched micro-network of interconnects, generally known as Network-on-Chip (NoC) architecture can be designed as regular or application-specific (irregular) network topologies. Application specific custom network topologies are advantageous in terms of optimized design according to given performance metrics and regular network topologies are advantageous in terms of its modularity, lower design time and efforts required and thus are suitable for mass production. So to offer the advantages of both the topologies this paper proposes a methodology to augment the regular topology according to the application characteristics. The experimental results demonstrate that the proposed methodology can reduce dynamic communication energy consumption by on average of 32.79% and reduction in average per flit latency by on average of 16.22% over regular 2D NoC architecture.

References

20 Cites in Article
  1. W Dally,B Towles (2001). Route packets, Not wires: On-chip interconnection networks.
  2. Umamaheswari,Rajapaul Perinbam (2011). Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures.
  3. Yu Bei,Dong Sheqin (2010). Floorplanning and Topology Generation for Application-Specific Network-on-Chip.
  4. H Fuks,A Lawniczak (1999). Performance of data networks with random links.
  5. Y Ogras Umit,R Marculescu (2005). Application Specific Network-on-Chip Architecture Customization via Long Range Link Insertion.
  6. Y Ogras Umit,R Marculescu (2006). It's a Small World After All: NoC Performance Optimization via Long Range Link Insertion.
  7. N Choudhary,M Gaur,V Laxmi,V Singh (2011). GA based congestion aware topology generation for application specific NoC.
  8. A Kahng,B Li,L Peh,K Samadi (2009). Orion 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
  9. R Dick,D Rhodes,W Wolf (1998). TGFF: task graphs for free.
  10. H Thomas,Charles Cormen,Ronald Leiserson,Clifford Rivest,Stein (2009). Introduction to Algorithms.
  11. B George (2009). Energy consumption in networks on chip: efficiency and scaling.
  12. M Dehyadgari,M Nickray,A Kusha,Z Navabi (2005). Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NOC.
  13. José Duato,Sudhakar Yalamanchili,Lionel Ni (2003). Introduction.
  14. Naren Tikare (2011). Routing Packets On A Chip : Network On Chip Algorithm.
  15. G Adamu,P Chejara,A Garko,B (2015). Review of deterministic routing algorithm for network-onchip.
  16. R Holsmark,M Palesi,S Kumar (2006). Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.
  17. N Choudhary (2012). Network-on-Chip: A New SoC Communication Infrastructure Paradigm.
  18. K Vyas,N Choudhary,D Singh (2013). NC-G-SIM: A Parameterized Generic Simulator for 2D-Mesh, 3D Mesh & Irregular On-chip Networks with Table-based Routing.
  19. P Wadhwani,N Chaudhary,D Singh (2013). Energy Efficient Mapping in 3D Mesh Communication Architecture for NoC.
  20. J Hu,R Marculescu (2003). Energy-aware mapping for tile-based NoC architectures under performance constraints.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Samta Jain. 2016. \u201cAn Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks\u201d. Global Journal of Computer Science and Technology - E: Network, Web & Security GJCST-E Volume 16 (GJCST Volume 16 Issue E3): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords
Classification
GJCST-E Classification: C.1.2, C.2.0, C.2.1
Version of record

v1.2

Issue date

May 12, 2016

Language
en
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On-chip communication, modular, scalable packet-switched micro-network of interconnects, generally known as Network-on-Chip (NoC) architecture can be designed as regular or application-specific (irregular) network topologies. Application specific custom network topologies are advantageous in terms of optimized design according to given performance metrics and regular network topologies are advantageous in terms of its modularity, lower design time and efforts required and thus are suitable for mass production. So to offer the advantages of both the topologies this paper proposes a methodology to augment the regular topology according to the application characteristics. The experimental results demonstrate that the proposed methodology can reduce dynamic communication energy consumption by on average of 32.79% and reduction in average per flit latency by on average of 16.22% over regular 2D NoC architecture.

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An Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks

Samta Jain
Samta Jain Maharana Pratap University of Agriculture and Technology
Vaishali Sodani
Vaishali Sodani
Naveen Choudhary
Naveen Choudhary

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