An Evolution of Parallel Pipeline System with the Classification of Operation Code

Dr. Narasimha Rao Yamarthi; Adinew Belay; Mr Abdisa L

doi:M4N5G655

An Evolution of Parallel Pipeline System with the Classification of Operation Code

Dr. Narasimha Rao Yamarthi * §

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Adinew Belay

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Mr Abdisa L

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mahesh781991

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§ Mizan Tepi University

An Evolution of Parallel Pipeline System with the Classification of Operation Code

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M4N5G655

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References

15 Cites in Article

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Eby G. Friedman,Mulligan (1991). Pipeliing of high performance synchronous digital systems.
C Gray,W Liu,R Cavin (1994). Timing constraints for wave-pipelined systems.
Yin Yong-Sheng,D Gao-Ming,Song Yu-Kun (2008). Study on the Multi-pipeline Reconfigurable Computing System.
Narasimha Rao,Y,Samuel Varaprasada Raju,G (2014). Enhancing Data Fetching Rates with Parallel Pipeline.
David Patterson,John Lhennessy (2005). Related Titles from Morgan Kaufmann Publishers.
Narasimha Rao,Y,Dr Samuel,Vara Prasada Raju,G Penmetsa,Krishna Raja (2014). ASIC Design, Implementation and Exploration on High Speed.
N Kumar,Rama Kotireddy,D,Pramod Kumar,B,Chaitanya Prabhu (2010). Two Way Clock Scheme in Pipeline to Minimize the Clock Skew.
Glenn Mehdi Hatamian,L Cash (1986). A 70-MHz 8-bit X 8bit Parallel Pipelined Multiplier in 2.5-pm CMOS.
G Eby,Friedman (2001). Clock Distribution Networks in Synchronous Digital Integrated Circuits.
K Suresh (2016). Optimizing Technique to Improve the Speed of Data Throughput through Pipeline.
K Compton,S Hauck (2002). Reconfigurable Computing: A Survey of Systems and Software.
N Kumar,D Kotireddy (2015). Measurement system for wide range frequency at nonlinear devices.
K Hwang (1993). Adrnnced Computer Architecture with Pllrallel Programming.
C Kozyrakis,D Patterson (2003). Scalable vector processors for embedded systems.
N Kumar,D Kotireddy (2011). A New Method to Enhance Performance of Digital Frequency Measurement and Minimize the Clock Skew.

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Dr. Narasimha Rao Yamarthi, Adinew Belay, Mr Abdisa L, mahesh781991. 2018. "An Evolution of Parallel Pipeline System with the Classification of Operation Code". Global Journal of Computer Science and Technology - B: Cloud & Distributed GJCST-B Volume 18 (GJCST Volume 18 Issue B1).

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GJCST Volume 18 Issue B1

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

Classification classified instruction cycle method peline processing speed data systems Throughput

Classification

GJCST-B Classification B.2.1

C.1.3

Submission ReceivedDecember 8, 2017
Peer Review Double Blind
Handling Editor
Accepted December 31, 2017
Published January 15, 2018

Version of record

v1.2

Issue date

June 8, 2018

Language

English

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46 cited on this article

Total Score: 119

Country: Ethiopia

Subject: Global Journal of Computer Science and Technology

Authors: Dr. Narasimha Rao Yamarthi, Adinew Belay, Mr Abdisa L, Mr Mahesh Nelapati (PhD/Dr. count: 1)

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Publish Date: 2018 01, Mon

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Total Downloads: 85

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