An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

1
Rajeshwari Soma
Rajeshwari Soma
2
Zulekha Tabassum
Zulekha Tabassum
3
S.Prathap
S.Prathap
1 JNTUH

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This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

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Not applicable for this article.

Rajeshwari Soma. 2013. \u201cAn On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers\u201d. Global Journal of Computer Science and Technology - C: Software & Data Engineering GJCST-C Volume 13 (GJCST Volume 13 Issue C10): .

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GJCST Volume 13 Issue C10
Pg. 21- 28
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Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

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v1.2

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October 5, 2013

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English

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This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

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An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

Rajeshwari Soma
Rajeshwari Soma JNTUH
Zulekha Tabassum
Zulekha Tabassum
S.Prathap
S.Prathap

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