Neural Networks and Rules-based Systems used to Find Rational and Scientific Correlations between being Here and Now with Afterlife Conditions
Neural Networks and Rules-based Systems used to Find Rational and
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This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.
Rajeshwari Soma. 2013. \u201cAn On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers\u201d. Global Journal of Computer Science and Technology - C: Software & Data Engineering GJCST-C Volume 13 (GJCST Volume 13 Issue C10): .
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
The methods for personal identification and authentication are no exception.
Total Score: 103
Country: India
Subject: Global Journal of Computer Science and Technology - C: Software & Data Engineering
Authors: Rajeshwari Soma, Zulekha Tabassum, S.Prathap (PhD/Dr. count: 0)
View Count (all-time): 209
Total Views (Real + Logic): 9324
Total Downloads (simulated): 2393
Publish Date: 2013 10, Sat
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This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.
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