An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

Rajeshwari Soma

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Zulekha Tabassum

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S.Prathap

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Jawaharlal Nehru Technological University, Hyderabad

An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

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Abstract

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

References

14 Cites in Article

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Rajeshwari Soma. 2013. \u201cAn On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers\u201d. Global Journal of Computer Science and Technology - C: Software & Data Engineering GJCST-C Volume 13 (GJCST Volume 13 Issue C10).

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GJCST Volume 13 Issue C10

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

delay estimation design for testability (DFT)integrated circuit measurements semiconductor device reliability signature register

Submission ReceivedDecember 14, 2012
Peer Review Double Blind
Handling Editor
Accepted December 31, 2012
Published January 15, 2013

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v1.2

Issue date

October 5, 2013

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Article Matrices

Total Score: 103

Country: India

Subject: Global Journal of Computer Science and Technology - C: Software & Data Engineering

Authors: Rajeshwari Soma, Zulekha Tabassum, S.Prathap (PhD/Dr. count: 0)

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Total Downloads: 2450

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