Area Optimized Low Latency Karatsuba Ofman Multiplier Variant for Embedded ECC

1
Sunil Devidas Bobade
Sunil Devidas Bobade
2
Dr.Vijay R. Mankar
Dr.Vijay R. Mankar
1 S.G.B.Amravati University

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GJRE Volume 15 Issue J3

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Area Optimized Low Latency Karatsuba Ofman Multiplier Variant for Embedded ECC Banner

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The objective of our study was to evaluate, in a population of Togolese People Living With HIV(PLWHIV), the agreement between three scores derived from the general population namely the Framingham score, the Systematic Coronary Risk Evaluation (SCORE), the evaluation of the cardiovascular risk (CVR) according to the World Health Organization.
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Due to resource constrains, implementation of secure protocols for securing embedded systems has become a challenging task. System designers are advised to design and install area efficient versions of existing, proven security protocols. System designers are finding ways and means to compress existing security protocols without compromising security and without tampering with basic security structure of algorithm. Modular multiplication, point multiplication, point doubling are few critical activities to be carried out in ECC algorithm. By optimizing Modular Multiplier, area efficiency in ECC algorithm can be achieved. In this paper, we propose Area optimized and low latency multiplier that implements the efficient KOA algorithm in altogether novel style to be used in ECC architecture. The proposed algorithm uses a novel technique of splitting input operands based on exponent’s parity and it eventually helps in reducing FPGA footprint and offers low latency by avoiding overlapping, prime concern for any embedded system. The complete modular multiplier and the crypto processor module is synthesized and simulated using Xilinx ISE Design suite 14.4 software. We have investigated area occupancy of proposed multiplier and crypto processor and concluded that proposed scheme occupies relatively reduced percentage area of FPGA as compared to the one using traditional KOA multiplier.

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8 Cites in Articles

References

  1. Hossein Mahdizadeh,Massoud Masoumi (2013). Novel architecture for efficient FPGA implementation of elliptic curve cryptographic processor over GF(2 163 ).
  2. Sunil Devidas,Bobade Dr,R Vijay,Mankar (2015). Low footprint Hybrid Finite field multiplier for Embedded cryptography.
  3. Roy Rebeiro,C Mukhopadhyay,D (2013). Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed.
  4. Jarvinen Azarderakhsh,M Mozaffari-Kermani (2014). Efficient algorithm and architecture for elliptic curve cryptography for extremely constrained secure applications.
  5. Kazuo Sakiyama,Miroslav Knežević,Junfeng Fan,Bart Preneel,Ingrid Verbauwhede (2011). Tripartite modular multiplication.
  6. Roy Rebeiro,C Mukhopadhyay (2013). Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed.
  7. R Azarderakhsh,K Karabina (2013). A New Double Point Multiplication Algorithm and its Application to Binary Elliptic Curves with Endomorphisms.
  8. A Kaleel Rahuman,G Athisha (2013). Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

Sunil Devidas Bobade. 2015. \u201cArea Optimized Low Latency Karatsuba Ofman Multiplier Variant for Embedded ECC\u201d. Global Journal of Research in Engineering - J: General Engineering GJRE-J Volume 15 (GJRE Volume 15 Issue J3): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

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GJRE-J Classification: FOR Code: 291899
Version of record

v1.2

Issue date

May 8, 2015

Language

English

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Area Optimized Low Latency Karatsuba Ofman Multiplier Variant for Embedded ECC

Sunil Devidas Bobade
Sunil Devidas Bobade S.G.B.Amravati University
Dr.Vijay R. Mankar
Dr.Vijay R. Mankar

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