ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier
Designing multiplier is always a challenging and interesting job, in order to satisfy user needs as per demand.Vedic multiplier is prominent system for faster result and optimized circuit design. In any digital system the throughput and power consumption decides the performance. The present work mainly concentrated on Vedic multiplier power consumption and throughput. In much faster computing and parallel processing architectures, pipeline motivates for higher throughput. This is motivated to incorporate pipeline in the present work to enhance the performance of the Vedic multiplier. In the present paper, area and power consumption is also taken into consideration along with throughput. These parameters are compared for different fast adders such as RCA, CSLA, LFA, BKA, KGA in Vedic multiplier. The Vedic multipliers are designed and analysed using Cadense RTL Compiler v08.10.
