ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier

Y. Narasimha Rao

ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier

Y. Narasimha Rao * §

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GITAM University

ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier

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Abstract

Designing multiplier is always a challenging and interesting job, in order to satisfy user needs as per demand. Vedic multiplier is prominent system for faster result and optimized circuit design. In any digital system the throughput and power consumption decides the performance. The present work mainly concentrated on Vedic multiplier power consumption and throughput. In much faster computing and parallel processing architectures, pipeline motivates for higher throughput. This is motivated to incorporate pipeline in the present work to enhance the performance of the Vedic multiplier. In the present paper, area and power consumption is also taken into consideration along with throughput. These parameters are compared for different fast adders such as RCA, CSLA, LFA, BKA, KGA in Vedic multiplier. The Vedic multipliers are designed and analysed using Cadense RTL Compiler v08.10.

References

10 Cites in Article

Reference Format

1. Rakshith Saligram (2013). Optimized Reversible Vedic Multipliers for High Speed Low Power Operations. Proceedings of 2013 IEEE Conference on Information and Communication Technologies, 809-814.
2. Jagadguru Swami,Sri Bharath,Krsna Tirathji (1986). Vedic Mathematics or Sixteen Simple Sutras From The Vedas. Vedic Mathematics or Sixteen Simple Sutras From The Vedas
3. G Kumar (2012). Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques. International Journal of Scientific and Research Publications, 2(3), 1-5.
4. Y Narasimharao (2014). Area Efficient High Speed Vedic Multiplier. International Journal of Innovative Technology and Exploring Engineering, 8(9S), 302-306.
5. Y Narasimharao (2014). Studies and Performance Evaluation of Vedic Multiplier using Fast Adders. IJCET, 4(3), 1908-1912.
6. D Hoe (2011). Design and characterization of parallel prefix adders using FPGAs. IEEE, 43rd Southeastern Symposium on System
7. J Desiree (2013). Fast and Area Efficient RSA Cryptosystem Design Using Modified Montgomery Multiplication for FPGA Applications. IJSER, 4(7)
8. Unknown Title.
9. G Jyoshna (2011). Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. UACEE International journal of Advances in Electronics Engineering, 1(1)
10. K Sreenath (2012). Reconfigurable VLSI architecture for FFT computation. IJSER, 3(6)

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Y. Narasimha Rao. 2014. "ASIC Design, Implementation and Exploration on High Speed Parallel Multiplier". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F6).

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GJRE Volume 14 Issue F6

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

Area fast adders pipeline power consumption Throughput vedic multiplier

Classification

GJRE-F Classification FOR Code: 100699

Submission ReceivedDecember 16, 2013
Peer Review Double Blind
Handling Editor
Accepted January 4, 2014
Published January 15, 2014

Version of record

v1.2

Issue date

August 16, 2014

Language

German

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Article Matrices

Total Score: 78

Country: Ethiopia

Subject: Global Journal of Research in Engineering

Authors: Y. Narasimha Rao, DR. G. Samuel Vara Prasada Raju, Penmetsa V Krishna Raja (PhD/Dr. count: 1)

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Publish Date: 2014 01, Wed

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Total Views: 950

Total Downloads: 81

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