Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Article ID

1O7AY

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Y. Sreenivasula Goud
Y. Sreenivasula Goud JNTU, Hyderabad.
Dr.B.K.Madhavi
Dr.B.K.Madhavi
DOI

Abstract

Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.

Y. Sreenivasula Goud
Y. Sreenivasula Goud JNTU, Hyderabad.
Dr.B.K.Madhavi
Dr.B.K.Madhavi

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Y. Sreenivasula Goud. 2013. “. Global Journal of Research in Engineering – F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F7): .

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Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

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Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Y. Sreenivasula Goud
Y. Sreenivasula Goud JNTU, Hyderabad.
Dr.B.K.Madhavi
Dr.B.K.Madhavi

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