Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Y. Sreenivasula Goud

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Dr.B.K.Madhavi

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Jawaharlal Nehru Technological University, Hyderabad

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

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Abstract

Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.

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The authors declare no conflict of interest.

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How to Cite This Article

Y. Sreenivasula Goud. 2013. \u201cBench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F7).

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GJRE Volume 13 Issue F7

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Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

ate bist inte-grated circuit(ic)low power testing very large scale integration (VLSI)

Submission ReceivedDecember 7, 2012
Peer Review Double Blind
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Accepted January 3, 2013
Published January 15, 2013

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May 26, 2013

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Total Score: 107

Country: India

Subject: Global Journal of Research in Engineering - F: Electrical & Electronic

Authors: Y. Sreenivasula Goud, Dr.B.K.Madhavi (PhD/Dr. count: 1)

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