Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language

Adesh Kumar; Pooja Nagwal; Dhirendra Singh Gangwar

Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language

Adesh Kumar * §

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Pooja Nagwal

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Dhirendra Singh Gangwar

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University of Petroleum and Energy Studies Dehradun,...

Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language

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Abstract

The paper focuses on the design and synthesis of hardware chip for Spatio and Viterbi encoding and decoding techniques. Both techniques are used for digital data encoding and decoding in transmitter and receiver respectively. These techniques are used for error control coding found in convolution codes. Spatio coding is also used to eliminate crosstalk among interconnect wires, thereby reducing delay. The encoded data is in packet form may be of ‘N’ bits. Data is decoded at different clock pluses at which it is encoded. A comparative analysis is done for hardware parameter, timing parameters and device utilization. Design is implemented in Xilinx 14.2 VHDL software, and functional simulation was carried out in Modelsim 10.1 b, student edition. Hardware parameters such as size cost and timings are extracted from the design code.

References

16 Cites in Article

Reference Format

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Adesh Kumar, Pooja Nagwal, Dhirendra Gangwar. 2013. "Comparative Analysis of Spatio and Viterbi Encoding and Decoding Techniques in Hardware Description Language". Global Journal of Computer Science and Technology, Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 13 (GJCST Volume 13 Issue A1).

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GJCST Volume 13 Issue A1

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

field programmable gate array (FPGA)register transfer level (RTL)very high speed integrated circuit hardware description language (VHDL)very lar

Classification

GJCST-A Classification B.m

Submission ReceivedDecember 10, 2012
Peer Review Double Blind
Handling Editor
Accepted January 4, 2013
Published January 15, 2013

Version of record

v1.2

Issue date

August 1, 2013

Language

English

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Article Matrices

Total Score: 143

Country: India

Subject: Global Journal of Computer Science and Technology

Authors: Pooja Nagwal, Adesh Kumar, Dhirendra Singh Gangwar (PhD/Dr. count: 0)

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Publish Date: 2013 01, Tue

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