Design and FPGA Implementation of High Speed DWT-IDWT Architecture with Pipelined SPIHT Architecture for Image Compression
Image compression demands high speed architectures for transformation and encoding process. Medical image compression demands lossless compression schemes and faster architectures. A trade-off between speed and area decides the complexity of image compression algorithms. In this work, a high speed DWT architecture and pipelined SPIHT architecture is designed, modeled and implemented on FPGA platform. DWT computation is performed using matrix multiplication operation and is implemented on Virtex-5 FPGA that consumes less than 1% of the hardware resource. The SPIHT algorithm that is performed using pipelined architecture and hence achieves higher throughput and latency. The SPIHT algorithm operates at a frequency of 260 MHz and occupies area less than 15% of the resources. The architecture designed is suitable for high speed image compression applications.
