1. Naoki Fujieda,Takefumi Miyoshi,Kenji Kise -A: Introduction to the MIPS32® Architecture. MIPS® Architecture For Programmers, 3
2. MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture. MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture
3. MIPS® Architecture For Programmers Volume II-A: Introduction to the MIPS32® Architecture. MIPS® Architecture For Programmers Volume II-A: Introduction to the MIPS32® Architecture
4. (2005). Porting Applications. Embedded Linux System Design and Development, 193-228.
5. Simple Scalar Simulator Toolset. Simple Scalar Simulator Toolset
6. Mohammad-Ali Khalighi,Noah Schwartz,Naziha Aitamer,Salah Bourennane (2009). Fading Reduction by Aperture Averaging and Spatial Diversity in Optical Wireless Systems. Journal of Optical Communications and Networking, 1(6), 580.
7. A Aladeloba,A Phillips,M Woolfson (2012). Performance evaluation of optically preamplified digital pulse position modulation turbulent freespace optical communication systems. IET Optoelectronics, 6, 66-74.
8. L Andrews,R Phillips,C Hopen (2000). Aperture averaging of optical scintillations: power fluctuations and the temporal spectrum. Waves Random Media, 10, 53-70.
9. S Bloom,E Korevaar,J Schuster,H Willebrand (2003). Understanding the performance of freespace optics. Journal of Optical Networking, 2, 178-200.
10. D Borah,D Voelz (2009). Pointing error effects on free-space optical communication links in the presence of atmospheric turbulence. Journal of Lightwave Technology, 27, 3965-3973.
11. Ahmed Farid,Steve Hranilovic (2007). Outage Capacity Optimization for Free-Space Optical Links With Pointing Errors. Journal of Lightwave Technology, 25(7), 1702-1710.
12. H Sandalidis,T Tsiftsis,G Karagiannidis,M Uysal (2015). BER Performance of FSO Links over Strong Atmospheric Turbulence Channels with Pointing Errors. IEEE Communications Letters, 12(1), 44-46.
13. N Choudhary,S Wadhavkar,T Shah,H Mayukh,J Gandhi,B Dwiel,S Navada,H Najaf-Abadi,E Rotenberg (2008). FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores Within a Canonical Superscalar Template. Proceedings of the 38th Annual International Symposium on Computer Architecture, 12, 44-46.
14. A Phillips (2007). Power penalty for burst mode reception in the presence of interchannel crosstalk. IET Optoelectronics, 1, 127-134.
15. K Cattermole,J O'reilly (1984). Mathematical topics in telecommunications volume 2: problems of randomness in communication engineering. Mathematical topics in telecommunications volume 2: problems of randomness in communication engineering
16. I Monroy,E Tangdiongga (2002). Crosstalk in WDM communication networks. Crosstalk in WDM communication networks
17. J O'reilly,J Da Rocha (1987). Improved error probability evaluation methods for direct detection optical communication systems. IEEE Transactions on Information Theory, 33, 839-848.
18. L Ribeiro,J Da Rocha,O Pinto (2001). Performance evaluation of EDFA preamplified receivers taking into account intersymbol interference. Journal of Lightwave Technology, 13(2), 225-232.
19. Smith James,Plezskun Andrew,R (1988). Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers, 37(5), 562-573.
20. Wang Chia-Jiu,Emnett Frank (1993). Implementing Precise Interruptions in Pipelined RISC Processors. IEEE, Micro, 13(4), 36-43.
21. Ke Xi-Ming (2003). Implementation Mechanism of Precise Interrupts in Microprocessors. High Performance Computing Technology, 160, 45-48.
22. Zhang Chen,Sheng-Bing,Shen Xu-Bang (2007). New precise interrupt mechanism based on backup-buffer. Computer Engineering and Applications, 43(6), 95-98.
23. Liu Shibin,Fan Gaodeyuan,Xiaoya (2001). Design of Instruction Decoder for Use in China for an Embedded MPU. Design of Instruction Decoder for Use in China for an Embedded MPU, 19, 1-5.
24. D Anderson,F Sparacio,F Tomasulo (1967). The IBM systeml360 Model 91 : Machine philosophy and instruction handling. IBM 1. Res. Develop, 11, 8-24.
25. E Ozer,S Sathaye,K Menezes,S Banerjia,M Jennings,T Conte (1998). A fast interrupt handling scheme for VLIW processors. Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 136-141.
26. E Smith,A Pleszkun (1988). Implementing precise interrupts in pipelined processors. IEEE Trans. Comput, C(5), 562-573.
27. W-M Hwu,Y Patt (1987). Checkpoint Repair for Out-of-Order Execution Machines. IEEE Trans. Computers, C(2), 522.
28. M Pericas,A Cristal,R Gonzalez,D Jimenez,M Valero (2006). A decoupled KILO-instruction processor. High-Performance Computer Architecture
29. Dominic Sweetman (2002). MIPS Architecture. See MIPS Run, 29-52.
30. John David A Patterson,Hennessy (1998). Morgan Kaufmann Publishers, Inc. IEEE Software, 3(2), 95-95.
31. Stephen Brown,Zvonkovranesic (2000). Fundamentals of Digital Logic with VHDL Design. Fundamentals of Digital Logic with VHDL Design
32. Zhu Ziyu,Li Yamin (2005). Design of Computer Instruction Set and The CPU. CPU Chip Logic Design, 237-298.
33. (2011). Altera university program-Learning through innovation. Altera university program-Learning through innovation
34. A Clements (2000). The undergraduate curriculum in computer architecture. IEEE Micro, 20(3), 13-21.
35. J Djordjevic,B Nikolic,T Borozan,A Milenkovie (2008). CAL2: Computer aided learning in computer architecture laboratory. Comput. Appl. Eng. Educ, 16, 172-188.
36. Bosko Nikolic,Zaharije Radivojevic,Jovan Djordjevic,Veljko Milutinovic (2009). A Survey and Evaluation of Simulators Suitable for Teaching Courses in Computer Architecture and Organization. IEEE Transactions on Education, 52(4), 449-458.
37. H Oztekin,F Temurtas,A Gulbag (2010). BZK.SAU: Implementing a hardware and software-based computer architecture simulator for educational purpose. Proc. 2nd Int. Conf. Comput. Design Appl, 490-497.
38. Veselko Guštin,Patricio Bulić (2006). Learning computer architecture concepts with the FPGA-based “Move” microprocessor. Computer Applications in Engineering Education, 14(2), 135-141.
39. lui r1, 0 # address of data. lui r1, 0 # address of data
40. Unknown Title. ori r4
41. (5, r). Figure 6—figure supplement 2. Measurement of Yan-YFP noise in all cell types. -extended : 0000ffff A: xori r8, r8, 0x5555#zero-extended : 0000aaaa B: addi r9, r0, -1 # sign-extended :ffffffff
42. C andi r10, r9, 0xffff # zero-extended : 0000ffff D: or r6, r10, r9 # or: ffffffff. andi r10, r9, 0xffff # zero-extended : 0000ffff D: or r6, r10, r9 # or: ffffffff
43. E (, r5). xor r8, r10, r9 # xor: ffff0000 F: and r7, r10, r6 # and: 0000ffff 10: beq r5, r0, shift # if r5 =0, goto shift 11: dslot2:nop # DS 12: j loop2 # jump loop2 13: dslot3: nop # DS 14: shift: addi r5, r0, -1 # r5 = ffffffff 15: sll r8. xor r8, r10, r9 # xor: ffff0000 F: and r7, r10, r6 # and: 0000ffff 10: beq r5, r0, shift # if r5 =0, goto shift 11: dslot2:nop # DS 12: j loop2 # jump loop2 13: dslot3: nop # DS 14: shift: addi r5, r0, -1 # r5 = ffffffff 15: sll r8
44. Unknown Title. # SysCall handler 10: epc_plus4: mfc0 r26, C0_EPC # get EPC 11: addi r26, r26, 4 #EPC + 4 : mtc0 r26, C0_EPC #EPC EPC +4 13: eret #return from exception 14: nop 15: uni_entry: nop 16: j epc_plus4 #return 17: nop 1a: ovf_entry: nop #overflow handler 1b: j epc_plus4 #return 1c: nop 1d: start: addi r8, r0, 0xf # IM[3:0] 1111 1e: mtc0 r8, C0_STATUS # exc/intr enable, 16.
