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ReserarchID
PU203
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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This paper attempted to assess the attitudes of students in
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Image compression is one of the major applications in image processing that imposes greater design challenges for VLSI design engineers in design and development of low power and high speed architectures. DWT is used in image compression for transformation of image from spatial to frequency domain. In this paper, DWT architecture based on lifting scheme is considered and dynamic power reduction is achieved with suitable modifications to the architecture and adoption of low power techniques. The interdependency of scaling and dilation coefficients is simplified to single hierarchy and thus reduces latency and increases throughput. Wallace tree multiplier and carry select adder are used in realizing 1D DWT architecture. The hierarchy in the design enables to adopt multi-stage and hierarchical clock gating technique thus reducing dynamic power. Power gating and DVFS techniques are also adopted to optimize power dissipation.
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