Energy Efficient Branch and Bound based On-Chip Irregular Network Design

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Kalpana Jain
Kalpana Jain
σ
Naveen Choudhary
Naveen Choudhary
ρ
Dharm Singh
Dharm Singh
α Maharana Pratap University of Agriculture and Technology Maharana Pratap University of Agriculture and Technology

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Energy Efficient Branch and Bound based On-Chip Irregular Network Design

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Abstract

Here we present a technique which construct the topology for heterogeneous SoC, (Application Specific NoC) such that total Dynamic communication energy is optimized. The topology is certain to satisfy the constraints of node degree as well the link length. We first layout the topology by finding the shortest path between traffic characteristics with the branch and bound optimization technique. Deadlock is dealt with escape routing using Spanning tree. Investigation outcome show that the proposed design methodology is fast and achieves significant dynamic energy gain.

References

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Kalpana Jain. 2014. \u201cEnergy Efficient Branch and Bound based On-Chip Irregular Network Design\u201d. Global Journal of Computer Science and Technology - C: Software & Data Engineering GJCST-C Volume 14 (GJCST Volume 14 Issue C4): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Version of record

v1.2

Issue date

July 5, 2014

Language
en
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Here we present a technique which construct the topology for heterogeneous SoC, (Application Specific NoC) such that total Dynamic communication energy is optimized. The topology is certain to satisfy the constraints of node degree as well the link length. We first layout the topology by finding the shortest path between traffic characteristics with the branch and bound optimization technique. Deadlock is dealt with escape routing using Spanning tree. Investigation outcome show that the proposed design methodology is fast and achieves significant dynamic energy gain.

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Energy Efficient Branch and Bound based On-Chip Irregular Network Design

Kalpana Jain
Kalpana Jain Maharana Pratap University of Agriculture and Technology
Naveen Choudhary
Naveen Choudhary
Dharm Singh
Dharm Singh

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