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CSTSDEMK248
Here we present a technique which construct the topology for heterogeneous SoC, (Application Specific NoC) such that total Dynamic communication energy is optimized. The topology is certain to satisfy the constraints of node degree as well the link length. We first layout the topology by finding the shortest path between traffic characteristics with the branch and bound optimization technique. Deadlock is dealt with escape routing using Spanning tree. Investigation outcome show that the proposed design methodology is fast and achieves significant dynamic energy gain.
Kalpana Jain. 2014. \u201cEnergy Efficient Branch and Bound based On-Chip Irregular Network Design\u201d. Global Journal of Computer Science and Technology - C: Software & Data Engineering GJCST-C Volume 14 (GJCST Volume 14 Issue C4): .
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
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Total Score: 103
Country: India
Subject: Global Journal of Computer Science and Technology - C: Software & Data Engineering
Authors: Kalpana Jain,Naveen Choudhary, Dharm Singh (PhD/Dr. count: 0)
View Count (all-time): 269
Total Views (Real + Logic): 8975
Total Downloads (simulated): 2297
Publish Date: 2014 07, Sat
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Here we present a technique which construct the topology for heterogeneous SoC, (Application Specific NoC) such that total Dynamic communication energy is optimized. The topology is certain to satisfy the constraints of node degree as well the link length. We first layout the topology by finding the shortest path between traffic characteristics with the branch and bound optimization technique. Deadlock is dealt with escape routing using Spanning tree. Investigation outcome show that the proposed design methodology is fast and achieves significant dynamic energy gain.
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