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FPGA Implementation of NPSF Testing Using Block Code Technique

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FPGA Implementation of NPSF Testing Using Block Code Technique

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Abstract

This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

References

12 Cites in Article
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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

K.L.V.Ramana Kumari, M. Asha Rani, N.Balaji, shaiksalauddeen. 2018. "FPGA Implementation of NPSF Testing Using Block Code Technique". Global Journal of Computer Science and Technology - G: Interdisciplinary GJCST-G Volume 18 (GJCST Volume 18 Issue G3).

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords
Classification
GJCST-G Classification D.2.5
Version of record
v1.2

Issue date
June 9, 2018

Language
English
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FPGA Implementation of NPSF Testing Using Block Code Technique

K.L.V.Ramana Kumari
K.L.V.Ramana Kumari
M. Rani
M. Rani
N.Balaji
N.Balaji <p>Sreyas Institute of Engineering and Technology Affliated to JNTU Hyderabad</p>