FPGA Implementation of QMF for Equalizer Application of Wireless Communication Channel

Abstract

In this paper a Quadrature Mirror Filter is implemented in VHDL, for wireless communication applications. The Quadrature Mirror Filter (QMF) basically is a parallel combination of a High Pass Filter (HPF) and Low Pass Filter (LPF), which performs the action of frequency subdivision by splitting the signal spectrum into two spectra. The QMF implementation is carried out on FPGA platform. The Xilinx IP Core generator will be used for instantiating the standard Xilinx parts. Xilinx ISE will be used to carry out the synthesis and bit file generation. The obtained Synthesis Report for implemented QMF will be used to analyze the occupied area and power dissipation. The study and implementation will be aimed to realize the equalizer for wireless communication system. Modelsim Xilinx Edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis and bit file generation. The Xilinx Chip scope will be used to test the results on Spartan 3E 500K FPGA board.

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