Hardware Synthesis of Chip Enhancement Trasformations in Hardware Description Language Environment

Priyanka Saini; Adesh Kumar; Neha Singh

Hardware Synthesis of Chip Enhancement Trasformations in Hardware Description Language Environment

Priyanka Saini * §

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Adesh Kumar

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Neha Singh

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aks_826

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§ Institute of Engineering and Technology, Alwar Rajas...

Hardware Synthesis of Chip Enhancement Trasformations in Hardware Description Language Environment

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Abstract

Human analyze different sight in daily life images to perceive their environment. More than 99% of the activity of human brain is involved in processing images from the visual cortex. A visual image is rich in information and can save thousand words. Many real world images are acquired with low contrast and unsuitable for human eyes to read, such as industrial and medical X-ray images. Image enhancement is a classical problem in image processing and computer vision. The image enhancement is widely used for image processing and as a preprocessing step in texture synthesis, speech recognition, and many other image/video processing applications. The main challenge is to transpose the validated algorithms into a language as hardware description languages. It is also the need that the input and output data files should be reshaped to match the binary content permitted into the hardware simulators. Research focuses on Simulation, Design and Synthesis of 2D and 3D Image enhancement chip in Hardware description language (HDL) Environment. The chip implementation of image enhancement algorithm is done using Discrete Wavelet Transformation (DWT) and Inverse Modified Discrete Cosine Transformation (IMDCT). Hardware chip modeling and simulation is done in Xilinx 14.2 ISE Simulator. Synthesis environment is carried out on Diligent Sparten-3E FPGA. . Image enhanced values are seen in the waveform editor of Modelsim software.

References

21 Cites in Article

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Priyanka Saini, Adesh Kumar, Neha Singh, aks_826. 2013. "Hardware Synthesis of Chip Enhancement Trasformations in Hardware Description Language Environment". Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 13 (GJCST Volume 13 Issue A1).

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GJCST Volume 13 Issue A1

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

FPGAfield programmable gate array HE – histogram equalization VHDLvery high speed integrated circuit hardware description language

Classification

GJCST-A Classification B.7.0

Submission ReceivedDecember 6, 2012
Peer Review Double Blind
Handling Editor
Accepted January 1, 2013
Published January 15, 2013

Version of record

v1.2

Issue date

August 1, 2013

Language

English

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Article Matrices

Total Score: 149

Country: India

Subject: Global Journal of Computer Science and Technology

Authors: Priyanka Saini, Adesh Kumar, Neha Singh, Dr. Anil Kumar Sharma (PhD/Dr. count: 1)

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Publish Date: 2013 01, Tue

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Total Downloads: 199

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