Implementation of Extracted Timing Methodology on Process Monitor for Silicon Characterization

1
Bhagyasri Chandaka
Bhagyasri Chandaka
2
Dr. R.Ramana Reddy
Dr. R.Ramana Reddy
1 MVGR college of engineering

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Process variations are playing a key role in defining the behaviour of an IP. These process variations can accurately measure using process monitor. In order to verify process variations, the process monitor should meet all timing requirements. Static Timing Analysis (STA) uses best case/ and worst analysis overly pessimistic, and could be optimistic also in some cases. Static Timing Analysis (STA) is a method for estimating yield of a circuit in terms of timing activities. Model extraction is a technique that accurately captures the characteristics of interface logic of a design in the form of a timing library model and provides a capacity improvement in timing verification by more than two orders of magnitude. Extracted timing model is an efficient timing library model to get accurate timing arcs of the circuit. This paper describes Methodology for creating timing models and also the flow to develop IP (process monitor) ETMs (.lib) using Synopsys Primetime tool, which can be used in any SOC and ETMs (Extracted timing models)with necessary time-budgeting instead of IP Netlists. Generated ETM with and without annotation delays and compared the library file. And the process monitor’s ring oscillator is designed through Verilog code using cadence tool.

9 Cites in Articles

References

  1. K C Auguslikifli,Wu (2015). 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).
  2. Null- Wang,N Xu,S-O Toh,A Neureuther,T-J King Liu,B Nikolic (2010). Parameter-specific ring oscillator for process monitoring at the 45 nm node.
  3. Cristiano Forzan,Davide Pandini (2009). Statistical static timing analysis: A survey.
  4. W Cho,Moon (2002). Timing Model Extraction of Hierarchical Blocks by Graph Reduction.
  5. M Bhushan,A Gattiker,M Ketchen,K Das (2006). Ring Oscillators for CMOS Process Tuning and Variability Control.
  6. R Saleh,S Wilton,S Mirabbasi,A Hu,M Greenstreet,G Lemieux,P Pande,C Grecu,A Ivanov (2006). System-on-Chip: Reuse and Integration.
  7. Seok-Yoon Kim,N Gopal,L Pillage (1994). Time-domain macro models for VLSI interconnect analysis.
  8. Isaac Evgenikrimer,Keslassey,Avinoamkoladny,Mattanerez Lsaskharwalter Static timing analysis for modelling QoS in Network-on-chip.
  9. Parthapratinpande Cristiangrecu,Andre Lvanov,Res Saleh (2005). Timing analysis of network on chip architectures for MP-SOC platforms.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

Bhagyasri Chandaka. 2018. \u201cImplementation of Extracted Timing Methodology on Process Monitor for Silicon Characterization\u201d. Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 18 (GJCST Volume 18 Issue A1): .

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Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

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GJCST-A Classification: B.7.m
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December 24, 2018

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English

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Process variations are playing a key role in defining the behaviour of an IP. These process variations can accurately measure using process monitor. In order to verify process variations, the process monitor should meet all timing requirements. Static Timing Analysis (STA) uses best case/ and worst analysis overly pessimistic, and could be optimistic also in some cases. Static Timing Analysis (STA) is a method for estimating yield of a circuit in terms of timing activities. Model extraction is a technique that accurately captures the characteristics of interface logic of a design in the form of a timing library model and provides a capacity improvement in timing verification by more than two orders of magnitude. Extracted timing model is an efficient timing library model to get accurate timing arcs of the circuit. This paper describes Methodology for creating timing models and also the flow to develop IP (process monitor) ETMs (.lib) using Synopsys Primetime tool, which can be used in any SOC and ETMs (Extracted timing models)with necessary time-budgeting instead of IP Netlists. Generated ETM with and without annotation delays and compared the library file. And the process monitor’s ring oscillator is designed through Verilog code using cadence tool.

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Implementation of Extracted Timing Methodology on Process Monitor for Silicon Characterization

Bhagyasri Chandaka
Bhagyasri Chandaka MVGR college of engineering
Dr. R.Ramana Reddy
Dr. R.Ramana Reddy

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