Investigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications Using FPGAs

α
Pradeep N
Pradeep N
σ
Elango S
Elango S
ρ
Sampath P
Sampath P
Ѡ
Gayathri K
Gayathri K
α Bannari Amman Institute of Technology Bannari Amman Institute of Technology

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Investigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications Using FPGAs

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Abstract

Signed multiplication is a complex arithmetic operation, which is reflected in its relatively high signal propagation delay, high power dissipation, and large area requirement. High reliability applications such as Cryptography, Residue Number System (RNS) and Digital Signal Processing (DSP)’s effective performance is mainly depend on its arithmetic circuit’s performance. Trend of using Residue Number System (RNS) instead of Constrain over-whelming Binary representation is promising technique in VLSI Systems and Multiplier is the basic building block of such systems. In this paper we have considered signed Modified Baugh Wooley Multiplier and Modified Booth Encoding (MBE) Multiplier logic for analysis and synthesized on best suited application platform. Analysis has taken account of Delay, Number of Logic Element requirements; Number of Signal Transition for particular sample input and its Power Consumption were analyzed for both Modified Baugh Wooley Multiplier and Modified Booth Encoding Multiplier.

References

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Pradeep N. 2015. \u201cInvestigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications Using FPGAs\u201d. Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 15 (GJCST Volume 15 Issue A1): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords
Classification
B.7.1
Version of record

v1.2

Issue date

March 17, 2015

Language
en
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Signed multiplication is a complex arithmetic operation, which is reflected in its relatively high signal propagation delay, high power dissipation, and large area requirement. High reliability applications such as Cryptography, Residue Number System (RNS) and Digital Signal Processing (DSP)’s effective performance is mainly depend on its arithmetic circuit’s performance. Trend of using Residue Number System (RNS) instead of Constrain over-whelming Binary representation is promising technique in VLSI Systems and Multiplier is the basic building block of such systems. In this paper we have considered signed Modified Baugh Wooley Multiplier and Modified Booth Encoding (MBE) Multiplier logic for analysis and synthesized on best suited application platform. Analysis has taken account of Delay, Number of Logic Element requirements; Number of Signal Transition for particular sample input and its Power Consumption were analyzed for both Modified Baugh Wooley Multiplier and Modified Booth Encoding Multiplier.

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Investigating the VLSI Characterization of Parallel Signed Multipliers for RNS Applications Using FPGAs

Pradeep N
Pradeep N Bannari Amman Institute of Technology
Elango S
Elango S
Sampath P
Sampath P
Gayathri K
Gayathri K

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