Method to Minimize Data losses in multi stage Flip Flop

α
dr._n.suresh_kumar
dr._n.suresh_kumar
σ
N. Suresh Kumar
N. Suresh Kumar
ρ
Dr. D.V. Ramakoti Reddy
Dr. D.V. Ramakoti Reddy
Ѡ
Anil patro
Anil patro
¥
K.V.Ramana Rao
K.V.Ramana Rao
§
I.Krishnarao
I.Krishnarao
α GITAM University GITAM University

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Method to Minimize Data losses in multi stage Flip Flop

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Abstract

In complex digital circuits the clock arrives at next stages before the data pulses arrives to the next stage. The clock pulse must be inserted to activate the digital circuits at any stage starting from first stage. But due to unsynchronization between clock pulse and data there is a chance of miss hitting in the next stages. This leads improper data transmissions in complex systems. It creates data losses in transmission. In the present work a gate controlled clock scheme is proposed to increase data hitting ratio.

References

2 Cites in Article
  1. B Suryanarayana,Tatapudi,G José,Delgado-Frias (2006). Student Member.
  2. C Gay (1994). Timing constraints for wave pipelined systems.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

dr._n.suresh_kumar. 2011. \u201cMethod to Minimize Data losses in multi stage Flip Flop\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 11 (GJRE Volume 11 Issue F6): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Version of record

v1.2

Issue date

November 15, 2011

Language
en
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In complex digital circuits the clock arrives at next stages before the data pulses arrives to the next stage. The clock pulse must be inserted to activate the digital circuits at any stage starting from first stage. But due to unsynchronization between clock pulse and data there is a chance of miss hitting in the next stages. This leads improper data transmissions in complex systems. It creates data losses in transmission. In the present work a gate controlled clock scheme is proposed to increase data hitting ratio.

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Method to Minimize Data losses in multi stage Flip Flop

N. Suresh Kumar
N. Suresh Kumar
Dr. D.V. Ramakoti Reddy
Dr. D.V. Ramakoti Reddy
Anil patro
Anil patro
K.V.Ramana Rao
K.V.Ramana Rao
I.Krishnarao
I.Krishnarao

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