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In complex digital circuits the clock arrives at next stages before the data pulses arrives to the next stage. The clock pulse must be inserted to activate the digital circuits at any stage starting from first stage. But due to unsynchronization between clock pulse and data there is a chance of miss hitting in the next stages. This leads improper data transmissions in complex systems. It creates data losses in transmission. In the present work a gate controlled clock scheme is proposed to increase data hitting ratio.
N. Suresh Kumar. 2011. "Method to Minimize Data losses in multi stage Flip Flop". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 11 (GJRE Volume 11 Issue F6).
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
v1.2
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Total Score: 110
Country: Unknown
Subject: Global Journal of Research in Engineering
Authors: N. Suresh Kumar, Dr. D.V. Ramakoti Reddy, Anil patro, K.V.Ramana Rao, I.Krishnarao (PhD/Dr. count: 1)
View Count (all-time): 347
Total Views (Real + Logic): 2340
Total Downloads (simulated): 95
Publish Date: 2011 10, Tue
Monthly Totals (Real + Logic):
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