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Artificial Neural Networks (ANN) is significantly used in signal and image processing techniques for pattern recognition and template matching. Discrete Wavelet Transform (DWT) is combined with neural network to achieve higher compression if 2D data such as image. Image compression using neural network and DWT have shown superior results over classical techniques, with 70% higher compression and 20% improvement in Mean Square Error (MSE). Hardware complexity and power dissipation are the major challenges that have been addressed in this work for VLSI implementation. In this work, modified distributive arithmetic DWT and multiplexer based DWT architecture are designed to reduce the computation complexity of hybrid architecture for image compression. A 2D DWT architecture is designed with 1D DWT architecture and is implemented on FPGA that operates at 268 MHz consuming power less than 1W.
Mr. Murali Mohan.S. 2014. \u201cModified Distributive Arithmetic based 2D-DWT for Hybrid (Neural Network-DWT) Image Compression\u201d. Global Journal of Computer Science and Technology - F: Graphics & Vision GJCST-F Volume 14 (GJCST Volume 14 Issue F2): .
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
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Total Score: 107
Country: India
Subject: Global Journal of Computer Science and Technology - F: Graphics & Vision
Authors: Mr. Murali Mohan.S, Dr. P.Satyanarayana (PhD/Dr. count: 1)
View Count (all-time): 261
Total Views (Real + Logic): 8986
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Publish Date: 2014 06, Tue
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Artificial Neural Networks (ANN) is significantly used in signal and image processing techniques for pattern recognition and template matching. Discrete Wavelet Transform (DWT) is combined with neural network to achieve higher compression if 2D data such as image. Image compression using neural network and DWT have shown superior results over classical techniques, with 70% higher compression and 20% improvement in Mean Square Error (MSE). Hardware complexity and power dissipation are the major challenges that have been addressed in this work for VLSI implementation. In this work, modified distributive arithmetic DWT and multiplexer based DWT architecture are designed to reduce the computation complexity of hybrid architecture for image compression. A 2D DWT architecture is designed with 1D DWT architecture and is implemented on FPGA that operates at 268 MHz consuming power less than 1W.
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