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In the last decade, Networks-on-Chips became the leading edge technology due to the growing requirements of electronic systems. Basically, NoC is an advancement of bus interconnect technology. The challenge is to interconnect existing components such as processors, controllers, and memory arrays in such a way that there is an optimal utilization of communication resources necessitating optimization of the various dominant factors like energy/power consumption, interconnection delay, latency, throughput, etc. In this paper, we focused on the evolution of NoC. Then we studied and have shown through an example that when application specific long-range links are inserted among the tiles whose communication frequencies are high, there is a reduction in the average packet latency and an energy efficient architecture is build up with high throughput. We also discussed the turn model which is deadlock free and the energy model for NoC.
Vaishali Maheshwari. 2015. "NoC Evolution and Performance Optimization by Addition of Long Range Links: A Survey". Global Journal of Computer Science and Technology - E: Network, Web & Security GJCST-E Volume 15 (GJCST Volume 15 Issue E6).
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
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Total Score: 107
Country: India
Subject: Global Journal of Computer Science and Technology - E: Network, Web & Security
Authors: Vaishali Maheshwari, Dr. Naveen Choudhary (PhD/Dr. count: 1)
View Count (all-time): 482
Total Views (Real + Logic): 2054
Total Downloads (simulated): 132
Publish Date: 2015 03, Sun
Monthly Totals (Real + Logic):
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