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ReserarchID
26H72
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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The traditional platforms for implementing hearing aid algorithms have been application specific integrated circuits (ASIC) and some general purpose DSP chips. One of the most important issues involved in hearing aid design is power consumption, i.e., battery life. This paper introduces an alternative method for implementing hearing aid algorithms by using truncated-matrix multipliers. These designs can offer a significant reduction in power consumption and chip area. However, the approach can often increase computational error but it can be partially compensated for by introducing a method of coefficient shifting of the filter weights. This latter approach significantly reduces the computational error resulting in improved system performance.
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