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The traditional platforms for implementing hearing aid algorithms have been application specific integrated circuits (ASIC) and some general purpose DSP chips. One of the most important issues involved in hearing aid design is power consumption, i.e., battery life. This paper introduces an alternative method for implementing hearing aid algorithms by using truncated-matrix multipliers. These designs can offer a significant reduction in power consumption and chip area. However, the approach can often increase computational error but it can be partially compensated for by introducing a method of coefficient shifting of the filter weights. This latter approach significantly reduces the computational error resulting in improved system performance.
Thomas Hemminger, Thomas Hemminger. 2013. "Reducing Hearing Aid Power Consumption Using Truncated-Matrix Multipliers". Global Journal of Research in Engineering, Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F8).
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
v1.2
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Total Score: 132
Country: United States
Subject: Global Journal of Research in Engineering
Authors: Thomas L. Hemminger, E. George Walters (PhD/Dr. count: 0)
View Count (all-time): 322
Total Views (Real + Logic): 1797
Total Downloads (simulated): 137
Publish Date: 2013 01, Tue
Monthly Totals (Real + Logic):
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