Reducing Hearing Aid Power Consumption using Truncated Matrix Multipliers

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Reducing Hearing Aid Power Consumption using Truncated Matrix Multipliers

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Abstract

The traditional platforms for implementing hearing aid algorithms have been application specific integrated circuits (ASIC) and some general purpose DSP chips. One of the most important issues involved in hearing aid design is power consumption, i.e., battery life. This paper introduces an alternative method for implementing hearing aid algorithms by using truncated-matrix multipliers. These designs can offer a significant reduction in power consumption and chip area. However, the approach can often increase computational error but it can be partially compensated for by introducing a method of coefficient shifting of the filter weights. This latter approach significantly reduces the computational error resulting in improved system performance.

References

18 Cites in Article
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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Thomas L. Hemminger, E. George Walters. 2013. "Reducing Hearing Aid Power Consumption using Truncated Matrix Multipliers". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue 25 (F8)).

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords
Classification
GJRE-F Classification FOR Code: 090699
Version of record

v1.2

Issue date
June 18, 2013

Language
English
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Reducing Hearing Aid Power Consumption using Truncated Matrix Multipliers

Thomas Hemminger
Thomas Hemminger
E. Walters
E. Walters