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Recently, irregular sampling techniques have been proposed for the design of digital front-end of a radio receiver. This front-end consist in the interface between the analog front-end and the baseband processing. The advantage of these techniques is the simplification of the sampling frequency conversion and the channel selection. The objective of the proposed work is to study if a gain in power consumption is also obtained. In this paper, the major research is the digital-front-end power consumption by using random sampling. Firstly, we introduce the methods of random sampling JRS (Jitter random sampling) and ARS (Additive random sampling). Then we use these methods to generate the random clock, select the hardware as mixed platform with ADC and FPGA and implement different solutions. At last, we measure the power consumption of different solutions and make a comparison.
M. Diop. 2014. \u201cStudy of the Power Consumption of a Digital- Front-End using Random Sampling\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F3): .
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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Total Score: 103
Country: Senegal
Subject: Global Journal of Research in Engineering - F: Electrical & Electronic
Authors: M. Diop, Deng Xiaoyu, J.-F. Diouris (PhD/Dr. count: 0)
View Count (all-time): 218
Total Views (Real + Logic): 4745
Total Downloads (simulated): 2358
Publish Date: 2014 06, Mon
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Recently, irregular sampling techniques have been proposed for the design of digital front-end of a radio receiver. This front-end consist in the interface between the analog front-end and the baseband processing. The advantage of these techniques is the simplification of the sampling frequency conversion and the channel selection. The objective of the proposed work is to study if a gain in power consumption is also obtained. In this paper, the major research is the digital-front-end power consumption by using random sampling. Firstly, we introduce the methods of random sampling JRS (Jitter random sampling) and ARS (Additive random sampling). Then we use these methods to generate the random clock, select the hardware as mixed platform with ADC and FPGA and implement different solutions. At last, we measure the power consumption of different solutions and make a comparison.
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