VHDL Design of FPGA Arithmetic Processor
This paper involves the design and development of a single chip VHDL FPGA processor which performs all arithmetic and logical functions and the output is displayed by means of LCD interface. This processor can perform 2n number of operations, where n is the number of control bits. In this design, a 5 bit control input is used so that the processor is capable of performing up to 32 operations. The chip is designed to execute 21 operations for different specified functions and 11 more operations can be worked on for improvements and future works. Two data with a size of 8 to 16 bits can be applied as input and the results are obtained on 4 to 8 hexadecimal digits carrying 32 bits in all. A status flag is also designed with the features such as indication of overflow, carry, borrow and zero value. To implement the above design, Very High Speed Description Language simulation is required which can be performed using Altera or Xilinx softwares. Once the program has been developed, the authors demonstrate the feasibility of the proposed design by incorporating it into a FPGA chip and the required hardware can be brought into effect. The state of each output bit is shown by using Light Emitting Diodes. Based on users needs, more features can be added to the designed hardware without hindering the implemented one.
