Design and Implementation of Low Power 12-Bit 100-MS/S Pipelined ADC Using Open-Loop Residue Amplification
In this paper a high speed, low power 12-bit, analog-to-digital converter in CMOS 0.13 micron technology that makes it suitable for UWB is designed and implemented. For designing the particular ADC a bottom up hierarchical method is adopted. First according to the specification, the design of aspect ratio of the transistors used in our design is done. There were many challenges throughout the design process, including determining the matching requirements of the devices, investigating what percentage of segmentation to be used to design the whole system. For checking the functionality of the whole system a spice code is written using HSPICE by defining all blocks in the circuit as sub circuits. Then a schematic capture is done using schematic composer from virtuoso stating from bottom level to top level. Finally the layout for the complete ADC is done using Electric Layout editor. A 12-bit pipelined ADC that can operate at maximum frequency of 100 MSPS, and power consumption less than 70mW is designed and implemented.
