Design of a Novel Low-Power SRAM Column
A novel SRAM column was designed. SRAM column includes SRAM cell, column select circuit, precharging circuit, and sense amplifier. The transmission gates are used for word line access in place of pass transistors which rectify the voltage drop problem; also there is an NMOS switch at the bottom of the cell which restricts the short circuit current flowing through the cell during operation. Using the standard process parameters of the PTM 7nm transistor model the SRAM column was simulated by HSPICE. The simulation results indicate the proper logic operation of the column and also it shows the low power operation.
